Silicon Labs /EFR32MG22C224F512IM32 /RAC_S /SYMMDCTRL

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Interpret as SYMMDCTRL

31282724232019161512118743000000000000000000000000000000000000000000 (disable)SYMMDENRSDIG0 (Divideby1)SYMMDDIVRSDIG0 (rx_w_swctrl)SYMMDMODE

SYMMDMODE=rx_w_swctrl, SYMMDDIVRSDIG=Divideby1, SYMMDENRSDIG=disable

Fields

SYMMDENRSDIG

SYMMDENRSDIG

0 (disable): undefined

1 (enable): undefined

SYMMDDIVRSDIG

SYMMDDIVRSDIG

0 (Divideby1): undefined

1 (Divideby2): undefined

2 (Divideby4): undefined

3 (Divideby8): undefined

SYMMDMODE

SYMMDMODE

0 (rx_w_swctrl): undefined

1 (rx_wo_swctrl): undefined

2 (qnc_dsm2): undefined

3 (qnc_dsm3): undefined

4 (rxlp_wo_swctrl): undefined

5 (notuse_5): undefined

6 (notuse_6): undefined

7 (notuse_7): undefined

Links

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